E-Layout: Layout-Stage Logic Restructuring via RL-Optimized Equality-Saturated Graph Retrieval-Augmented Generation

What it claims

E-Layout restructures logic after placement rather than before it. It replaces maximum fanout-free cones (MFFCs) in a placed, unoptimized layout with functionally equivalent alternatives, then picks new gate sizes and locations for them. The paper is accepted at ICCAD '26 (November 2026, San Jose). The work was largely done at NVIDIA with HKUST. The headline result over a commercial physical design flow is 6% average TNS gain, 2% WNS gain and 1% area reduction across 9 designs. The authors argue that post-placement is the earliest stage with real physical data. Physical-aware synthesis relies on estimates, and sign-off/ECO stages leave less room to optimize.

How it works

The unit of rewriting is the MFFC. Logic inside an MFFC is not shared outside the cone, so a cone can be swapped without disturbing the rest of the circuit. Non-overlapping MFFCs are processed in parallel.

1. E-graph saturation only, no extraction. Each MFFC has its sizes and locations stripped and is saturated with a custom standard-cell rule set. There are three rule types. Type I does one-level decomposition and recomposition of complex gates (AO22 ⇔ AO21 + AND2). Type II converts between complex cells and primitives (XOR2 ⇔ OR/AND/INV). Type III does Boolean simplification (De Morgan, double inversion, absorption). Standard e-graph extraction uses linear costs such as node count or depth, which cannot model placement-dependent NLDM delay. Extraction is therefore delegated to the next step.
2. Graph RAG. A layout encoder and a logic encoder retrieve a candidate structure from the saturated set. A decoder then generates each new cell's size and (x, y) location.
3. RL tuning. The RAG model is fine-tuned with RL on full-chip TNS. This step selects the set of disjoint restructurings that helps design-level timing, rather than judging each cone alone. The authors say graph RAG inference takes seconds per RL iteration.

flowchart LR
  P[Placed layout] --> M[Extract MFFCs]
  M --> E[E-graph saturation]
  E --> R[Graph RAG: pick structure, size, location]
  R --> T[Full-chip timing / TNS]
  T -- RL reward --> R
  R --> C[Commercial tool: legalize, buffer, size]

The restructured layout goes back to the commercial tool for incremental legalization and normal buffering and sizing. E-Layout adds to that flow and does not replace it.

Evidence

The comparison with open-source tools is qualitative (Table 1). OpenROAD's restructure calls ABC for remapping with unit delay and no physical awareness, which the authors say breaks physical coherence. OpenPhySyn only does pin-swap and gate cloning and makes no logic change. E-Layout rewrites logic at the subcircuit level and evaluates with layout NLDM delay. The authors rate its optimization space "medium", between the other two. The fetched text does not include the per-design results or the names of the 9 designs.

Limits

The fetched text stops partway through Section 4.1. It does not include the RAG architecture details, the RL formulation, the experimental setup, ablations, runtime totals or per-design tables. The commercial baseline tool and the cell library are not named in the text shown. The text mentions no code, model or rule-set release. The 6%/2%/1% figures are averages, and their spread across designs is not given here. Equivalence is claimed "by construction" from the rewrite rules. The text describes no separate formal check of the final netlist.