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Hardware-Level Mitigation of Micro-Architectural Leakages in Embedded Processors
eprint.iacr.orgpaper

Hardware-Level Mitigation of Micro-Architectural Leakages in Embedded Processors

Proposes RTL-level architectural changes to general-purpose processors that remove the root causes of micro-architectural leakage, so masked cryptographic software runs securely under the Robust but Relaxed (RR) d-probing model without security-aware compilers or hardware-specific software workarounds. Each countermeasure is formally proven secure and integrated into the Ibex RISC-V core, which is evaluated by tool-assisted leakage assessment of the full netlist and by physical measurements on an FPGA.

TL;DR RTL changes to the Ibex core eliminate micro-architectural leakage at the source, letting masked software stay secure under the RR d-probing model, with formal proofs, netlist assessment and FPGA tests.
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Organisations named here

  • TCHES

Technologies named here

  • Ibex processor
  • Tool-assisted leakage assessment of the full netlist
  • Field Programmable Gate Array
  • FPGA
  • Ibex

Techniques named here

  • Side-Channel Analysis
  • Masking countermeasure
  • Micro-architectural leakage
  • Robust but Relaxed d-probing model
  • Secure hardware-software co-design
  • Secure compilation
  • Formal security proofs of each countermeasure
  • Tool-assisted leakage assessment
  • Physical leakage experiments on FPGA

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