eprint.iacr.orgpaper

Area-Efficient Hardware Architecture of the Post-Quantum HQC Cryptosystem with Side-Channel Protection

This IACR eprint paper presents a resource-efficient FPGA hardware architecture for the NIST-selected HQC post-quantum KEM that defends against power-based side-channel attacks by reusing otherwise-idle KECCAK hardware to inject scrambling dynamic power during decoding, adding less than 0.5 percent area overhead compared to masking/shuffling countermeasures. The fully parameterized design supports HQC-128/192/256 and was prototyped on a Xilinx Artix-7 FPGA (139 MHz, 11,489 LUTs, 6,785 FFs, 4 DSPs), with functional correctness verified via NIST Known Answer Tests and leakage suppression confirmed via Test Vector Leakage Assessment.