eprint.iacr.orgpaperEnjoy FAEST on Hardware: Efficient and Novel Hardware Acceleration of Emerging Post-Quantum Digital Signature Scheme FAEST
This ePrint paper (2026/2525, October 2026) by Brendan Funk and Jiafeng Xie presents the first hardware accelerator for FAEST, an MPC-in-the-head post-quantum signature in NIST's Round 3 additional-signature process. It analyses FAEST's compute-heavy operations, builds them into hardware blocks, and adds an L1-EM-fast variant. The authors report at least 98% lower equivalent area-delay product than the recent complete SDitH design at the same security level.
TL;DR Presents the first FPGA accelerator for the FAEST post-quantum signature, reporting at least 98% lower area-delay product than a complete SDitH design.
Organisations named here
- L1-EM-fast
- MPC-in-the-head
Technologies named here
- FAEST hardware accelerator
- FAEST
- FPGA
- NIST
- SDitH
- Post-quantum cryptography
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