Side-Channel Attack Prevention for Post Quantum Cryptography Algorithms: A 3D-Shield Approach

What it is

A 31 October 2026 arXiv preprint (2611.01144v1) from Carl Benda, Eren Kurshan, Aydin Aysu and Paul Franzon (NC State, Princeton). It proposes a 3D-stacked "guard layer" die that runs decoy NTT cores next to the protected PQC die. The aim is to make a power-analysis attacker pick a wrong key. Evidence is software simulation only. No silicon or FPGA result exists yet.

How it works

The guard die shares a fine-grain vertical power grid with the crypto die, in face-to-face or face-to-back stacking. The paper argues this makes the decoy and real activity hard to separate. A decoy core processes the same input polynomial with a hardwired wrong twiddle factor.

The test setup is a simulated Kyber NTT over Z_3329 (N=256) with a Hamming-weight power proxy. The attack is Brier-style CPA on Layer 4 butterfly 0, with 2,000 traces and 128 twiddle candidates. The target is ZETAS[7]=848.

Preconditions / Affected

The threat model is a non-adaptive external power-measurement adversary with no knowledge of the decoy parameters. The design needs 3D integration (TSV-pitch power grid) and extra decoy cores on a second die. The paper claims no firmware changes, no NTT modifications and no functional latency overhead on the main die.

Caveats

• The authors say the defense must still be assessed against adversaries who recognise the decoy and try to separate it from real leakage. That was not tested.
• The simulation is ideal and noise-free, and uses a Hamming-weight model, not measured traces.
• The attacked values are public twiddle factors inside the butterfly. The paper concedes that real attacks usually target coefficient-wise multiplication after the NTT, where known inputs meet fixed secrets. It says the approach "can be extended" to that case and to single-trace attacks, but shows neither.
• Only Kyber's NTT was simulated. The ML-DSA, FN-DSA and SLH-DSA coverage in the summary rests on the background discussion, not on experiments.
• Power overhead, decoy core count and the cost of suppression are left to future work, as is FPGA evaluation.
• The text I received cuts off in the reference list, so any later content is not covered.