eprint.iacr.orgpaperSparse Secrets, Dense Problems: Efficiently Masking HQC in Hardware
ePrint paper presenting the first fully masked hardware implementation of HQC (key generation, encapsulation, decapsulation) on FPGA. It introduces a mixed Boolean/arithmetic masking for sparse-dense vector multiplication, proven first-order secure in the transition- and glitch-robust probing model and PINI-composable, at only 3% extra cycles and 81 random bits per cycle. It also shows a profiled horizontal side-channel attack on Rotate-and-Add multipliers that recovers support indices within ±8 positions from 200 traces despite TVLA showing no leakage after 10 million traces, and adds integrated hiding countermeasures costing 1.7% latency.
TL;DR First fully masked HQC hardware design with probing-model proofs; a horizontal attack breaks Rotate-and-Add multipliers from 200 FPGA traces despite clean TVLA, countered by built-in hiding.
Organisations named here
- horizontal side-channel attack
- PINI
- Rotate-and-Add
Technologies named here
- Masked fixed-weight samplers for HQC
- FPGA implementation of HQC
- Masked HQC decoder
- First fully masked hardware implementation of HQC
- HQC
- ML-KEM
- FPGA
- TVLA
- NIST
- Artix-7
Techniques named here
- Timing and power side-channel attacks against HQC
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