
Guess My Weight: Profiled Side-Channel Recovery of Floating-Point Neural-Network Weights
Researchers present a profiled template attack that recovers the bit-exact IEEE-754 single-precision representation of a neural-network weight from power traces captured during inference on an embedded device. Using multivariate Gaussian templates built from Hamming-weight leakage classes and a hierarchical coarse-to-fine-to-exact search over the 32-bit floating-point space, the attack achieves 99% bit-exact recovery with 171 traces and 100% from 263 traces on a ChipWhisperer-Lite with an Arm Cortex-M4, demonstrating practical full-precision model-weight extraction from physical side-channel leakage.
What it is
A profiled template attack targeting the specific floating-point multiplication v = float32(w⋆ · x) performed during the first-layer forward pass of a feed-forward neural network on an STM32F303 (ChipWhisperer-Lite, Arm Cortex-M4). The target weight in the experiment is 1.43 (stored as the nearest float32, bit pattern 0x3FB70A3D); the network has layers of 7, 5, 4, 3 neurons with ReLU hidden layers and a sigmoid output.
How it works
The attacker knows the architecture and controls the input x fed to the first neuron (other inputs fixed at 0.5, biases zero). Profiling: 50,000 traces are collected across 500 randomized network configurations (weights drawn from [-2,2], refreshed every 100 traces), with the target weight known for each trace, to build multivariate Gaussian templates over Hamming-weight leakage classes of the IEEE-754 product. Attack: for each candidate weight ŵ, the attacker computes the hypothetical product float32(ŵ·x), maps it to a leakage class, and scores it against the measured trace via accumulated template log-likelihood across traces. A key implementation detail: the firmware is compiled with -mfloat-abi=soft, so despite the MCU having a hardware FPU, every multiply runs through a software library routine that processes sign/exponent/fraction via integer instructions — this is what makes the operation leak in a structured, exploitable way. Because the 32-bit float space is too large to search directly, a hierarchical coarse-to-fine-to-exact procedure first resolves candidates using only the most significant bits, then progressively increases bit resolution to disambiguate numerically close float32 values in the final exact stage.
Preconditions / Affected
Requires: physical access to measure power consumption during inference; a same-model profiling device programmable with attacker-chosen weights; attacker control over at least one network input value; knowledge of network architecture and the position of the targeted multiplication. Demonstrated specifically against a software (soft-float) multiplication routine on Cortex-M4 — the leakage model depends on this soft-float execution path rather than hardware FPU instructions.
Caveats
Only the first weight of the first fully-connected layer is targeted; the paper notes this weight is uniquely favorable because one multiplication operand is directly attacker-chosen, whereas later-layer weights depend on prior activations that are generally unknown without already recovering earlier parameters. Non-target weights are randomized during profiling but not modeled explicitly — treated as tolerated nuisance variables rather than something the method explicitly compensates for.
Technologies named here
- Arm Cortex-M4
- ChipWhisperer-Lite
- Neural-network weights
- ChipWhisperer
Techniques named here
- Profiled template attack
- Hierarchical coarse-to-fine-to-exact candidate search
- Power side-channel analysis of floating-point multiplication
Related in Hardware & RF

HAETAE on a Diet: Less Stack, Less Time on Low-End Microcontrollers
geo-tp/ESP32-Bit-Pirate
