Randomized Caches in Hardware: Challenges and Trade-offs

What it is

A hardware study by Xinrui Wang, Pascal Kosak, Christof Paar, Daniel Genkin, Yuval Yarom and Anirban Chakraborty (arXiv 2611.00282, 30 October 2026). It implements CEASER-S, ScatterCache, SassCache and MIRAGE as the shared LLC of a multi-core out-of-order NaxRiscv RISC-V SoC on FPGA. Linux boots on each variant, and SPEC CPU 2017 rate and GAPBS run to completion, averaging 290 billion instructions per benchmark with some above one trillion. The authors say this is the first side-by-side comparison on one full-system platform. Earlier hardware work covered only one design each (CEASER and ScatterCache variants) on the in-order RocketChip core.

How it works

The baseline LLC relies on three properties that randomization breaks:

• Operations and hazard checks work per set, so the MSHR lock detects conflicts by comparing set indices alone.
• Tags and metadata for all ways sit in one wide SRAM word.
• Data and metadata live in separate arrays, so metadata updates do not wait behind multi-cycle refills (64-bit memory interface, 64-byte lines).

Skewed indexing gives each way or skew its own index, so conflict detection needs per-way comparison and the metadata can no longer be read as one wide word. The paper adds that relocation (CEASER-S) and indirection (MIRAGE) create asynchronous operation paths beyond the normal access pipeline.

Findings that matter for a decision

• Frequency: with the IDF already pipelined, drops range from 1% (ScatterCache) to 35% (MIRAGE). The paper attributes the large drops to asynchronous operations: relocation in CEASER-S and indirection in MIRAGE.
• Fix: the authors redesigned the critical paths of SassCache, CEASER-S and MIRAGE, keeping mappings, rekeying and victim selection unchanged. All three end within 10% of baseline frequency, paying with extra LLC latency or reduced concurrency (cache locking).
• IPC: LLC access latency dominates, not extra misses. Adding three cycles to a plain set-associative cache, matching the IDF latency of ScatterCache and MIRAGE, reproduces most of the loss. IPC loss tracks LLC access rate and reaches up to 10% on memory-intensive workloads. SassCache is the exception, because dynamic partitioning shrinks effective capacity.
• Combined effect: frequency and IPC losses together cut maximum execution throughput by up to 35%.
• Area: FPGA LUTs rise 10-35%, ASIC area 1-14%. The paper says overhead varies by resource, design and technology.

What to do

Do not budget a randomized LLC from a pipelined-IDF latency estimate alone. Check the critical paths of relocation, indirection and set-locking logic, and compare simulator IPC claims against the 5% (SPEC) and 11% (GAPBS) hardware figures.

Caveats

• The fetched text stops partway through Section III. The per-design solutions, the Section V critical-path details and the per-design numbers in Section VI are not available here.
• Results come from one core (NaxRiscv) and one FPGA flow. The ASIC area figures are given without method in the available text.
• The security properties of the designs were not re-evaluated; the study fixes each design's mappings, rekeying and victim selection.