eprint.iacr.orgpaper

A Security-Aware PQC Benchmarking Framework on Dual-Core Xtensa Silicon

This IACR ePrint paper proposes a security-aware benchmarking framework for deploying memory-heavy PQC (ML-KEM, ML-DSA) on the dual-core ESP32-S3 (Xtensa LX7) running FreeRTOS, aimed at smart-grid substation devices bound by the IEC 61850 GOOSE tripping window (≤3ms). It details an asymmetric task-isolation design pinning crypto to Core 1, a heap-auditing methodology for FreeRTOS's heap_4.c allocator tracking key-state allocations across DRAM, and an analytical latency model of CPU stall overhead caused when side-channel masking forces secret polynomial shares to spill to external Octal-SPI PSRAM during non-sequential Cooley-Tukey NTT strides. The work gives embedded engineers a methodology to evaluate PQC side-channel/latency trade-offs before migrating real-time grid infrastructure.